Förderjahr 2019 / / ProjektID: / Projekt: Introduction to nMigen.
The core nMigen project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python language. It aims to be easy to learn and use, reduce common coding mistakes, and simplify the hardware’s design.
The nMigen toolchain consists of:
the nMigen language
the standard library
the build system
1. The nMigen language
The nMigen hardware description language is a Python library for register transfer level modeling of synchronous logic. Ordinary Python code is used to construct a netlist of a digital circuit, which can be simulated, directly synthesized via Yosys_, or converted to human-readable Verilog code for use with industry-standard toolchains. By relying on the elegance, rich functionality and widespread adoption of the Python language, the nMigen language is focused on a single task: modeling digital logic well. It has first-class support for building blocks like clock domains and finite state machines and uses simple rules for arithmetic operations that closely match the Python semantics. Python classes, functions, loops and conditionals can be used to build organized and flexible designs.
2. The nMigen standard library
The nMigen language comes with a standard library-a collection of essential digital design components and interfaces. It includes clock domain crossing primitives, synchronous and asynchronous first ins, first outs (FIFO), a flexible input/output (I/O) buffer interface, and more. By providing reliable building blocks out of the box, nMigen allows the designer to focus on their application and avoids subtle differences in behavior between different designs. High-speed designs usually require the use of registered (and sometimes, geared) I/O buffers. The nMigen standard library provides a common interface to be used between I/O buffers and peripheral implementations.
3. The nMigen simulator
The nMigen project includes an advanced simulator for nMigen code implemented in pure Python. Although it is always possible to convert a nMigen design to Verilog for use with `Icarus Verilog`_ or Verilator_, the built-in simulator has no system dependencies and uses test benches implemented as Python generator functions.The nMigen simulator is event-driven and can simulate designs with multiple clocks or asynchronous reset and compiles the netlist to Python code when the simulation is started. Although nMigen does not support native code simulation or co-simulation at the moment, such support will be added in near future.
4. The nMigen build system
To achieve an end-to-end FPGA development workflow, the nMigen project integrates with all major FPGA toolchains and provides definitions for many common development boards. The nMigen build system directly integrates with every major open-source and commercial FPGA toolchain, and can be easily extended to cover others.
nMigen toolchain covers all steps of a typical FPGA development workflow and at the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an nMigen design flow, or, conversely, nMigen code can be integrated into an existing Verilog-based design flow.